1. Field of the Invention
The present invention relates to a reading circuit for semiconductor non-volatile memories.
More specifically, the invention relates to a reading circuit for semiconductor non-volatile memories connected to at least one selected cell and to at least one reference cell, comprising current/voltage conversion circuits receiving at the input thereof a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, as well as at least one differential amplifier, connected at the input of said first and second nodes and having an output terminal effective to supply the information stored in said selected cell.
The invention relates particularly, but non-exclusively, to a reading circuit for semiconductor non-volatile memories suitable for digital applications and implemented in CMOS technology, and the following description is given with reference to this field of application for convenience of illustration.
In particular, said circuit can be used both in conventional memories in which each memory element, or xe2x80x9cmemory cellxe2x80x9d, stores an information bit (generally referred to as xe2x80x9ctwo-level memoriesxe2x80x9d) and in memories in which each memory element is capable to store more than one bit (generally referred to as xe2x80x9cmultilevel memoriesxe2x80x9d).
Moreover, the circuit according to the invention can be used for information reading in non-volatile memories of the Flash, EPROM, EEPROM and OTP (One-Time Programmable) type.
2. Description of the Related Art
As is well known, a semiconductor non-volatile memory is a quite complex system. For example, as schematically shown in FIG. 1, a Flash memory 1, i.e., a memory whose cells are electrically programmable and erasable in great bulks, generally referred to as blocks or sectors, conventionally comprises:
a cell matrix 2, representing memory 1 core;
a decoding section, required to address the cells of the word to be selected during a particular programming or reading operation, as well as the sector or sectors to be erased during a particular erasing operation, and comprising essentially a line decoder 3 and a column decoder 4, both connected to said cell matrix 2;
a reading section, which performs the reading of the addressed cells and transmits the read data to output circuits, as well as an input/output section, which serves as interface for the insertion from the outside of the data to be stored in the addressed cells during a writing operation and for the transfer to the outside of the data concerning the read cells: said sections are schematically shown in FIG. 1 by means of a sense amplifier 5, regulators 6 connected to line decoders 3 and column decoders 4, and at least one output buffer 7 connected to said sense amplifier 5; and finally,
a supporting section comprising the circuits required to perform the above-described operations such as, for example, voltage step-up circuits 8 for generating the voltages required for performing programming and erasing operations in one-supply memories and connected to said regulators 6, a state machine for an appropriate timing of the various operations (not shown).
It is also worth noting that an EPROM memory is a quite complex system, even though less complex than a Flash memory since it does not comprise some of the above-mentioned blocks (such as, for example, voltage step-up circuits 8 and matrix cell erasing circuits, erasing being performed in this type of memories through ultraviolet ray exposure). Therefore, the comments made with reference to Flash memories apply also to EPROM memories.
It is worth remembering that the information storage, in the case of conventional two-level memory cells, corresponds to the conduction or shutdown state of a floating gate transistor, which are associated with the logic values xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. The two-level memory cell threshold voltage is high (Vthp) or low (Vthe) depending on the stored state, i.e., the charge stored in the floating gate terminal.
By using a greater number of charge values to be stored in the floating gate terminal than the two above-mentioned high and low threshold values, it is possible to increase the storage capacity, given the same cell size and technology. This is the case of xe2x80x9cmultilevelxe2x80x9d cells.
More particularly, by using, for example, four different charge levels, corresponding to four different floating gate transistor conduction states, two bits can thus be coded in one cell, doubling therefore the cell information content, given the same area covered by the cell and thus by the whole memory.
Multilevel cells are generally inserted in a NOR-type architecture, so that a state stored in a cell is effective to inhibit the floating gate transistor conduction included therein during a reading operation, as is the case with xe2x80x9c0xe2x80x9d programmed cells in two-level cell devices, the remaining states being such as to provide different conduction conditions of the selected cell.
In the above-mentioned case of four programmable levels (two bits per cell) the cell threshold voltage can have one of the four possible values Vth0, Vth1, Vth2, Vth3, a two-bit binary configuration corresponding to each value.
The advantages in terms of storage capacity provided by a multilevel cell memory are however accompanied by considerable problems. These problems are mainly due to the reduced difference between the different memory cell conduction levels, i.e., between the threshold voltages corresponding to the different charge levels which can be stored in the floating gate terminal of the transistors included in the memory cells.
Said reduced difference between the threshold voltage levels involves serious problems in terms both of design (for example of programming and reading circuits) and of reliability of the whole memory device.
More particularly, in known memory devices, the reading circuit (essentially a sense amplifier), performs the fundamental function of comparing two current values, the one delivered by a selected cell and the other by the corresponding reference cell, and of outputting a voltage level corresponding to said comparison result. In a two-level cell, sensing margins, considered as the lowest current difference detectable at the sense amplifier inputs, are conveniently relaxed and the current comparison is performed without endangering the reading speed. In the case of four-level cells, the allocation of the different state distributions imposes more severe requirements on the reading circuit design than in the conventional two-level cell case.
The multilevel cell reading circuits are therefore more constrained by the need for high sensitivity, in order to discriminate very small signal differences at the inputs thereof. This feature poses specific design problems linked to the need for accuracy and, moreover, it does not meet the high speed requirement of the reading circuit sense amplifier.
More particularly, the sense amplifier must necessarily be highly sensitive, without endangering the reading speed. In fact, the sense amplifier sensitivity must be lower than the minimum distance in current between the level distribution and the adjacent references thereto.
If a read path is considered, the information supplied by the sense amplifier, which performs, as above described, the function of showing the content of the addressed cell it refers to, is generally stored in a register or xe2x80x9clatchxe2x80x9d which drives the driving circuit or output buffer (xe2x80x9cdata output bufferxe2x80x9d), which performs the function of delivering the read data to external circuitries, which, according to the output buffer, can be modeled into a generally heavy capacitive load. The latch is generally used to keep the output buffer driving level constant for a predetermined period of time in order to make the output data transfer safe and reliable. The time instant for storing the information supplied by the sense amplifier must clearly be such as to ensure that the information outputted by the sense amplifier is correct, i.e., corresponding to the data stored in the non-volatile memory cell. In fact the sense amplifier takes a little time to output a voltage level being sufficiently high to be univocally interpreted and, thus, correctly stored in the latch.
In this respect, it is worth noting that a modern memory device comprises several output buffers suitable for simultaneous switching, and that the memory often comprises highly complex digital circuitry. Due to the commutations of these buffer outputs, which must generally drive considerably high capacitive loads (about 100pF), the commutations of the phase generator drivers for charge pumps and, sometimes, also the commutation of several memory logic gates, the memory supply lines (generally indicated by VDD and VSS) often undergo undesirable voltage peaks (xe2x80x9cglitchxe2x80x9d or xe2x80x9cspikexe2x80x9d) which generally make the lines highly noisy; said noise inevitably spreads over the whole memory circuitry and, particularly, also over the reading circuit sense amplifiers.
In order for the memory cell reading to be conveniently noise-insensitive, the voltage level outputted by the reading circuit sense amplifier when the data is stored in the latch must be sufficiently high: only then said voltage can be certainly distinguished from the noise, the corresponding information being thus correctly interpreted by the latch in which it is stored and, consequently, by the downstream output buffer.
The reading circuit sense amplifier immunity to noise is therefore essential for the correct operation of a semiconductor non-volatile memory.
Compromise design solutions between the above-described different needs are known.
For example, the process of dividing supply lines so that the reading circuit logic section has distinct and dedicated lines with respect to the analogue section lines, in order to reduce noises in said lines, is known.
Even with this expedient, the problem of noise in supply lines still exists, and it is still more evident in multilevel memories because of the reduced difference between the levels to be discriminated.
In addition, multilevel non-volatile memory reading circuits are based on the comparison between the cell current and the current of a conveniently programmed reference cell.
Such a solution is disclosed for example in European patent application no. 96830494.9 entitled xe2x80x9cReading circuit for semiconductor memory cellsxe2x80x9d filed in the name of the applicant for this invention and schematically shown in FIG. 2.
In said application, the discrimination between a memory cell current and a reference cell current is performed through the constant current capacity charge law. In particular, a current Iref flowing through the reference cell is compared with a current Isel flowing through the selected cell, said currents differing from each other by a minimum value which is equal to about 10 xcexcA in the case of four level cells implemented with present submicrometric technologies.
As shown in FIG. 2, the device 9 comprises two distinct circuit elements and, in particular, a pair of NMOS-type transistors MS1 and MS2 effective to ground the nodes X1 and X2 receiving said currents Iref and Isel respectively and connected to a ground reference GND by means of corresponding capacitors C1 and C2 which serve as integrators and are indicated by the reference numbers 9a and 9b. 
The transistors MS1 and MS2 are inserted between said nodes X1 and X2 and the ground reference GND and have control terminals cross-connected to the nodes X2 and X1 respectively. Therefore, said transistors MS1 and MS2 have a threshold voltage Vth and are controlled by the voltages Vref and Vsel of the nodes X1 and X2 and correlated to the reference cell current Iref and the selected cell current Isel.
It is worth noting that the presence of discharge transistors MS1 and MS2 avoids the simultaneous saturation of the voltages Vref and Vsel to the supply voltage VDD, so that the two voltages are then conveniently split, even when the transient is exhausted.
More particularly, since the two capacitors C1 and C2 serve as respective integrators 9a and 9b, identical in type and value, the highest voltage between Vref and Vsel at a predetermined time corresponds to the highest current between Iref and Isel. Therefore, one of the two nodes X1 and X2 achieves first the starting voltage of the corresponding discharge transistor MS1 or MS2, which, in this case, corresponds to the threshold voltage Vth. The discharge transistor MS1 or MS2 then activates the discharge of the node X1 or X2 with lowest voltage.
The voltage value activating a discharge transistor is referred to hereinafter as xe2x80x9cfreezing voltagexe2x80x9d since it determines the indefinite xe2x80x9cstoragexe2x80x9d of the information relating to the current comparison, which will be then detected through a differential amplifier AD having input terminals connected to said nodes X1 and X2 and an output terminal OUT.
Moreover, the discharge transistors MS1 and MS2 enable the storage of their difference sign and make the discrimination through the downstream differential amplifier AD more reliable. In fact, without avoiding the saturation of both voltages to the supply value VDD when transient is exhausted, it would be difficult to select the instant for storing in the downstream latch the information outputted by the sense amplifier. In fact, said instant must not be too advanced or suitable to ensure a sufficiently high signal value (equal to the module Vrefxe2x88x92Vsel) outputted by the sense amplifier; moreover, without avoiding the saturation of both voltages to the supply VDD, the instant for storing in the latch must not be too delayed since it would alter the correct data evaluation.
In other words, the determination of the data xe2x80x9cfreezingxe2x80x9d instant is quite difficult for this type of sense amplifier, also because of process and environmental/operating variations undergone by the reading circuit during the manufacturing and operation thereof.
Moreover, said known structure has some drawbacks. In particular, a prior art sense amplifier allows the correct evaluation of a difference |Vrefxe2x88x92Vsel| only if higher than a minimum value Vm, also referred to as xe2x80x9cmargin voltagexe2x80x9d. In general, the margin voltage Vm depends on both the accuracy of the input voltage of the differential amplifier AD and the noise margin associated to the input signals. For convenience, said value Vm corresponds to the voltage accuracy of a discrimination stage comprising a CMOS technology differential amplifier which equals, for example, to about 50 mV less the offset voltage.
The reading circuit sensitivity depends therefore on the voltage difference between Vref and Vsel.
On the contrary, the transistor MS1 and MS2 operation is based on a positive reaction, characterized by high speed. It is therefore necessary that this operation is activated when the absolute value of the difference |Vrefxe2x88x92Vsel| reaches a safety value, higher than the present electric noise. In the opposite case, the noise could trigger the positive reaction in a way opposite to the correct procedure, resulting then in a wrong reading.
In particular, for a correct discrimination, the transistor MS1 start-up (and, similarly, for transistor MS2) should be performed only after the detection of the voltage difference |Vrefxe2x88x92Vsel| by the differential amplifier AD.
With the above-described known circuit structure, the voltage required for starting the xe2x80x9cfreezingxe2x80x9d operation, or xe2x80x9cfreezing voltagexe2x80x9d, coincides then with the transistor NMOS threshold voltage Vth. Said reference value depends on both technologic (doping concentration, etc) and circuit (substrate-source voltage) factors. With the present submicrometric CMOS technologies, the threshold voltage Vth value of a low-voltage NMOS transistor is equal to about 0.7-0.8 V, while for the so-called natural transistors it is equal to about 0.1-0.3 V.
Taking into consideration values compatible with CMOS processes, for example Vth=700 mV, Isel=100 xcexcA, Iref=90 xcexcA, Vm=50 mV, it derives that Vsel=10*Vm=500 mV (independently of the capacity value). Said Vsel value is therefore quite near to the starting threshold value Vth of the MS1 transistor. Moreover, the voltage Vth is subject both to process variations (the threshold voltage in CMOS technology can vary even by +/xe2x88x9210%) and to environmental condition variations (the threshold voltage thermal drift in CMOS processes is of about xe2x88x922mV/degC).
All these aspects make thus the above-described known circuit structure intrinsically critical if the currents to be discriminated are reciprocally xe2x80x9cnearxe2x80x9d and relatively high in absolute value.
In fact, if the difference |Vrefxe2x88x92Vsel| value is still very low when the voltages Vref and Vsel reach values near to Vth, the electric noise can take the lowest of the two voltages Vref or Vsel above Vth, activating thus the positive reaction. In these cases, the time evolution of the voltage signals Vsel and Vref is inverted, a wrong information about the difference between the currents Isel and Iref being consequently stored.
For these reasons, a xe2x80x9cfreezingxe2x80x9d voltage value should be provided, which is adequately protected from process/environmental variations and particularly as much as possible immune to the noise of the memory device, differently from what happens in the prior art solution.
Briefly, known circuit solutions for reading (sensing) a non-volatile memory cell are not strong enough when electric noise is present in the device.
The technical problem underlying the present invention is to provide a reading circuit for non-volatile memories with such structural and functional characteristics as to overcome the drawbacks that still limit prior art reading circuits.
In particular, the reading circuit for non-volatile cells according to the invention has the following features:
high sensitivity,
low evaluation time, and
high noise immunity.
The circuit is therefore suitable for application particularly for multilevel memory reading, even if it can be efficiently applied also with conventional two-level memories.
The disclosed embodiments of the present invention provide, in a reading circuit, adequate dedicated circuit blocks in order to make the information discrimination reliable even when noises and/or electric noise are present.
A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell is provided. The reading circuit includes current/voltage conversion circuits receiving at the input a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage; at least one differential amplifier having inputs connected to the first and second nodes and having an output terminal effective to supply a logic signal correlated to the information contained in the selected cell; at least one first voltage-control discharge switch circuit connected to the input of the first node and to a voltage reference, a second voltage-control discharge circuit connected to the input of the second node and to the voltage reference; and at least a first and a second voltage comparator circuit receiving at the input thereof the first selected cell voltage and the second reference cell voltage, the comparator circuits configured to control in voltage the switch circuits.
In accordance with another aspect of the present invention, the comparator circuits are differential comparators of the module for absolute value of the difference between the selected cell voltage and the reference cell voltage with respect to a value corresponding to a tripping voltage for the start-up of the discharge switch circuits, the value being a fixed voltage reference.
The features and advantages of the reading circuit according to the invention will become apparent from the following description of embodiments thereof given by way of non limiting example with reference to the accompanying drawings.